The present invention relates to a wiring board.
FIG. 7 is a cross-sectional diagram showing an example of a configuration of a multilayer printed wiring board according to a related art.
Inside a wiring board shown in FIG. 7, at least one signal layer (Signal) 110S, at least one ground layer (GND) 110G, and at least one power plane (POWER PLANE) 110V are laminated with insulating layers (numerals omitted) interposed therebetween. A plurality of semiconductor packages 200 accommodating semiconductor device chips, such as LSI, are mounted over one substrate surface 121 (top surface of FIG. 7) of the wiring board 100. In the example shown, the semiconductor package 200 is a BGA (Ball Grid Array) package.
Inside the wiring board 100, there are at least one signal via 140S, composed of an opening in which an inner wall surface thereof is covered by a conductive material, that electrically conducts wiring 131 over one substrate surface 121 where a semiconductor package 200 is mounted, wiring 132 over the other substrate surface 122, and the signal layer 110S, at least one grand via 140G, composed of an opening in which an inner wall surface thereof is covered by the conductive material, that electrically conducts the wiring 131 over one substrate surface 121 where the semiconductor package 200 is mounted, the wiring 132 over the other substrate surface 122, and the ground layer 110G, and at least one power supply via 140V, composed of an opening in which an inner wall surface thereof is covered by the conductive material, that electrically conducts the wiring 131 over one substrate surface 121 where the semiconductor package 200 is mounted, the wiring 132 over the other substrate surface 122, and the power plane 110V.
A signal wiring 111S is formed inside the signal layer 110S of the wiring board 100. The signal wiring 111S performs signal transmission between the semiconductor packages 200.
As shown in FIG. 7, in the related art, the signal wiring 111S is disposed over the substrate surface 121 side where the semiconductor package 200 is mounted, and the power plane 110V is disposed below the signal wiring 111S. In this configuration, the section of the signal via 140S below the signal wiring 111S will be a stub 150, and parasitic capacitance divided from a signal transmission path is generated (see paragraph 0005 and FIGS. 4A and 4B of Japanese Unexamined Patent Application Publication No. 2005-183649). In the interface with transmission speed of Gbps or more, the parasitic capacitance generates waveform rounding due to this stub, which will be an obstacle in high-speed signal transmission.
Therefore, it has been suggested that the power plane is disposed near the substrate surface where a semiconductor device chip is mounted, signal wiring is disposed at a position as far as possible from the substrate surface where the semiconductor device chip is mounted, and the stub is shortened (see FIG. 3B in Japanese Unexamined Patent Application Publication No. 2005-183649, the signal wiring is denoted by the numeral 2). In the wiring board shown in the left and right diagrams of FIG. 8, the number of wiring layers is the same. However in the wiring board of the left diagram, a power plane is placed over the substrate surface where the semiconductor device chip is mounted.
The related arts of the present invention are; Japanese Unexamined Patent Application Publication Nos. H10-273254, H05-327172, H09-172261, and 2008-028188. The details of the related arts are described later.
In the wiring board, the section lower than the power plane of the power supply via is not actually required. The present inventor has found a problem that specially in the wiring board shown in the left diagram of FIG. 8 in which the power plane is disposed near the substrate surface where the semiconductor device chip is mounted, the section lower than the power plane of the power supply via occupies a large ratio and the existence thereof causes deterioration of wirability.
Especially when a high-density BGA package, which has solder balls (BGA terminals) pitched at 1.0 mm or less, is mounted, the pitch of the power supply via is small and the wiring design of the signal layer lower than the power plane and the other substrate surface side is limited.
With specific numeric values, if a BGA package of 1.0 mm pitch is mounted to a printed wiring board of 2.5 mm thickness, the hole diameter of the power supply via hole is 0.2 to 0.3 mm, the diameter of the via land provided on the other substrate surface side is about 0.4 to 0.6 mm, and the gap between adjacent via lands is about 0.4 to 0.6 mm. In this case, if two lines are placed between the adjacent via lands, the line width is about 100 μm at the maximum. Therefore, there are limitations in the number of channels and line width of the wiring on the signal layer lower than the power plane and the other substrate surface, thus there may be a mismatch in the impedance.
If the hole diameter of the power supply via is reduced, the pitch of the power supply via can be increased, and reservation of the number of wiring channels or impedance matching will be easy, but the resistance value of the power supply via increases and will be an obstacle in the power supply. Further, if the aspect ratio of the power supply via increases, it will be difficult to open the power supply via. Specifically, if the aspect ratio of the power supply via exceeds 20, it will be difficult to open the power supply via. For example, with the printed wiring board of 2.5 mm thickness, it is difficult to open a through hole with a 0.1 mm diameter (aspect ratio 25), relatively difficult to open a through hole with a 0.15 mm diameter (aspect ratio 16.6), and relatively easy to open a through hole with a 0.2 mm diameter (aspect ratio 12.5).